Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an unusually hardworking design verification engineer. As a member of our multifaceted group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day.This role is for a DV engineer who will enable us to produce fully functional first silicon for Analog/Digital mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.DescriptionIn this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage.Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches and track and report DV progress using a variety of metrics, including bugs and coverage.Minimum QualificationsBS degree in technical discipline with minimum 3 years of relevant experience.Preferred QualificationsDeep knowledge of SystemVerilog and UVM.Deep knowledge in developing scalable and portable test-benches.Proven experience with verification methodologies and tools such as simulators, waveform viewers.Build and run automation, coverage collection, gate level simulations.Some UVM knowledge, C/C++ level knowledge.Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR.Basic knowledge of formal verification methodology.Some experience with power-aware (UPF) or similar verification methodology.Knowledge of one of the scripting languages such as Python, Perl, TCL.
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